1. Field of the Invention
The present invention relates to a gate signal line drive circuit and a display device using the same, and more particularly, to noise suppression in the gate signal line drive circuit.
2. Description of the Related Art
In the related art, for example, in regard to a liquid crystal display device, there is disclosed a method in which a shift register circuit provided for a gate signal line drive circuit that scans a gate signal line is formed on the same substrate as thin film transistors (hereinafter, referred to as TFTs) that are disposed in a display region of a display screen, that is, a shift register-embedded method is adopted. As the shift register circuit according to the related art, shift register circuits disclosed in JP 2007-95190 A and JP 2008-122939 A are exemplified.
In each of a plurality of shift register basic circuits that are provided for the gate signal line drive circuit, at the time of a normal screen display, a high voltage is applied to a gate signal line as a gate signal Gn only for a gate scanning period (hereinafter, referred to as a signal high period), which corresponds to the gate signal line that is connected to the shift register basic circuit, in one frame period, and a low voltage is applied to the gate signal line as the gate signal Gn for a period (hereinafter, referred to as a signal low period) other than the gate scanning period.
FIG. 11 shows a simplified schematic diagram illustrating a configuration of the shift register basic circuit according to the related art. The shift register basic circuit is provided with a gate line low voltage applying circuit SWA that applies a low voltage to the gate signal line in response to the signal low period, and a gate line high voltage applying circuit SWG that applies a high voltage to the gate signal line in response to the signal high period.
A clock signal Vn of a predetermined cycle is input to an input side of the gate line high voltage applying circuit SWG. The gate line high voltage applying circuit SWG is turned on in response to the signal high period and a voltage of the clock signal Vn is applied to the gate signal line in order for a high voltage to be applied to the gate signal line for a signal high period. Here, the clock signal Vn is a clock signal that is set to a high voltage in the predetermined cycle and is set to the high voltage for the signal high period. In addition, the gate line high voltage applying circuit SWG is turned off in response to the signal low period and blocks a voltage of the clock signal Vn, and therefore the voltage of the clock signal Vn is not applied to the gate signal line. A voltage, which is applied to a switch of the gate line high voltage applying circuit SWG, is set at a node N1. The node N1 is set to an on-voltage while the gate line high voltage applying circuit SWG is in on-state, and therefore the on-voltage is applied to the switch of the gate line high voltage applying circuit SWG. In addition, the node N1 is set at an off-voltage while the gate line high voltage applying circuit SWG is in off-state, and therefore the off-voltage is applied to the switch of the gate line high voltage applying circuit SWG.
A low voltage line VGL, which is set to a low voltage, is connected to the input side of the gate line low voltage applying circuit SWA. The gate line low voltage applying circuit SWA is turned on in response to the signal low period and the low voltage of the low voltage line VGL is applied to the gate signal line in order for the low voltage to be stably applied to the gate signal line for the signal low period. In addition, the gate line low voltage applying circuit SWA is turned off in response to the signal high period. A voltage, which is applied to a switch of the gate line low voltage applying circuit SWA is set as a node N2. The node N2 is set to an on-voltage while the gate line low voltage applying circuit SWA is in on-state, and therefore the on-voltage is applied to the switch of the gate line low voltage applying circuit SWA. In addition, the node N2 is set to an off-voltage while the gate line low voltage applying circuit SWA is in off-state, and therefore the off-voltage is applied to the switch of the gate line low voltage applying circuit SWA.
FIG. 12 shows a circuit diagram of the shift register basic circuit according to the related art. Each of the transistors shown in FIG. 12 is an NMOS transistor, an on-voltage of each of the transistors is set to a high voltage, and an off-voltage is set to a low voltage. As shown in FIG. 12, a transistor T5 and a voltage-raising capacitor C1 correspond to the gate line high voltage applying circuit SWG. The node N1 is set to a high voltage in response to the signal high period, and a voltage of the clock signal Vn, which is input from an input terminal IN1, is applied to a gate signal line that is connected to an output terminal OUT and is output as a gate signal Gn.
In addition, as shown in FIG. 12, a transistor T6 corresponds to the gate line low voltage applying circuit SWA. The node N2 is held at a high voltage in response to the signal low period, and a low voltage of the low voltage line VGL is applied to the gate signal line that is connected to the output terminal OUT and the low voltage is output as the gate signal Gn.